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This page is to highlight important things to consider when porting the Renesas BSP to your own custom board.
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Overview
There is s a RZ/G2 Group Linux BSP Porting Guide document posted on Renesas.com.
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You do not normally need to modify many things in ATF and in any case only what is in the "plat/renesas/rz" folder. One of the first things ATF BL2 does is to configure the DDR. You would need to use the same (working) configuration used with Flash Writer, so there should be no surprise here, if the DDR works with Flash Writer then it will work with ATF as well.
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Then ATF loads BL31(image id=3), BL32 (again optionally, image id=4) and BL33 (u-boot, image id=5) from either QSPI or eMMC. Assuming everything goes fine u-boot prompt is finally reachable. The table below summarizes where the different actors in the boot process are typically stored and executed from.
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Finally you can use Yocto to generate the root file system including all the bits and bobs you need to run your custom application...
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Software Sections
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| When porting the BSP to a custom board, please refer to the section below in order. |
Github Repositories
- Please refer to the public source code repositories and branches to base your code from
- 👉 RZ BSP Github Repos
Flash Writer
When porting the BSP to a new board, start with this
sectionsoftware first
- Most important is getting DDR working before you move on to porting Trusted Firmware-A
- 👉 Please refer to page: RZ BSP Porting - Flash Writer
Trusted Firmware-A
Copy the DDR setting that you have working in Flash Writer
- 👉 Please refer to page: RZ BSP Porting - ARM Trusted Firmware
u-boot
u-boot
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will be loaded by Trusted Firmware-A
- 👉 Please refer to page: RZ BSP Porting - u-boot
Linux Kernel
- After u-boot is working, you can start to port the Linux kernel
- 👉 Please refer to page: RZ BSP Porting - Linux Kernel
Memory Map
This section explains how DDR Memory is divided and configured.
Software Update of Boot Loaders
Yocto
RZ/Five Instructions
Yocto
- 👉 Please refer to page: RZ BSP Porting - Yocto
Ubuntu
- Please refer to page: 👉 RZ BSP Porting - Ubuntu
OpenWRT
- Please refer to page: 👉 RZ BSP Porting - OpenWRT
Debian
- Please refer to page: 👉 RZ BSP Porting - Debian
Software Update
Memory Map
- This section explains how DDR Memory is divided and configured.
- RZ BSP Porting - Memory Map
Changing Console Port
You can make use of the following changes to change console port from SCIF0 to SCIF2 in RZ/G2L-LC and RZ/V2L (Not applicable for RZ/G2UL). Please note that it NOT RECOMMENDED by Renesas to do so and is described here only for experimental purpose.
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Trusted Firmware-A File: plat/renesas/rz/common/include/rzg2l_def.h #define RZG2L_SCIF0_BASE (0x1004B800) +#define RZG2L_SCIF2_BASE (0x1004C000) File: plat/renesas/rz/common/bl2_plat_setup.c initialize console driver */ ret = console_rzg2l_register( - RZG2L_SCIF0_BASE, + RZG2L_SCIF2_BASE, RZG2L_UART_INCK_HZ, RZG2L_UART_BARDRATE, &rzg2l_bl31_console); File: plat/renesas/rz/common/bl31_plat_setup.c initialize console driver */ ret = console_rzg2l_register( - RZG2L_SCIF0_BASE, + RZG2L_SCIF2_BASE, RZG2L_UART_INCK_HZ, RZG2L_UART_BARDRATE, &rzg2l_bl31_console); File: plat/renesas/rz/common/drivers/cpg.c { /* SCIF */
(uintptr_t)CPG_CLKON_SCIF,
(uintptr_t)CPG_CLKMON_SCIF,
- 0x001f0001,
+ 0x001f0004,
CPG_T_CLK
},
File: plat/renesas/rz/common/include/pfc_regs.h -#define PFC_MUX_TBL_NUM (4) +#define PFC_MUX_TBL_NUM (5) File: plat/renesas/rz/common/drivers/pfc.c { PFC_OFF, (uintptr_t)NULL, 0 } /* IEN */
+},
+/* P40(scif2) */
+{
+ { PFC_ON, (uintptr_t)PFC_PMC40, 0x1F }, /* PMC */
+ { PFC_ON, (uintptr_t)PFC_PFC40, 0x00011111 }, /* PFC */
+ { PFC_OFF, (uintptr_t)PFC_IOLH40, 0x0000000101010101 }, /* IOLH */
+ { PFC_OFF, (uintptr_t)PFC_PUPD40, 0x0000000000000000 }, /* PUPD */
+ { PFC_OFF, (uintptr_t)PFC_SR40, 0x0000000101010101 }, /* SR */
+ { PFC_OFF, (uintptr_t)NULL, 0 } /* IEN */
}
#endif
};
u-boot File: arch/arm/dts/smarc-rzg2l.dts aliases {
serial0 = &scif0;
+ serial1 = &scif2;
spi0 = &spibsc;
};
chosen {
- stdout-path = "serial0:115200n8";
+ stdout-path = "serial1:115200n8";
};
kernel File: arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi /* comment the #define statement to disable SCIF2 (SER0) on PMOD1 (CN7) */ -//#define PMOD1_SER0 1 +#define PMOD1_SER0 1 File: arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi chosen {
- stdout-path = "serial0:115200n8";
+ stdout-path = "serial1:115200n8";
+ bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
};
File: drivers/clk/renesas/r9a07g044-cpg.c static const unsigned int r9a07g044_crit_mod_clks[] __initconst = {
MOD_CLK_BASE + R9A07G044_IA55_PCLK,
MOD_CLK_BASE + R9A07G044_IA55_CLK,
MOD_CLK_BASE + R9A07G044_DMAC_ACLK,
+ MOD_CLK_BASE + R9A07G044_SCIF2_CLK_PCK,
}; |
Github Repositories
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- https://github.com/renesas-rz/rz_linux-cip
- https://github.com/renesas-rz/renesas-u-boot-cip
- https://github.com/renesas-rz/rzg2_flash_writer
- https://github.com/renesas-rz/rzg_trusted-firmware-a
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How to Build Outside of Yocto
The easiest and recommended way to build is by using these scripts. Otherwise you can install the toolchain as per these instructions and build manually following the instructions provided case by case.
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Overview
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