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The Link Status input pin (LINKSTA) is not used. The driver instead relies on the PHY to inform it that the link is up by using in-band status messages on the RGMII lines.
Do not forget to set the correct voltage levels for the pins (3.3v, 1.5v, etc..) in the device tree in the pinctrl node.
- You use the syntax "power-source = <3300>;" when you declare the pins for Ethernet. If an Ethernet PHY supports multiple voltages (3.3v or 1.8v), then choose the lower voltage because the Electrical Characteristics are better.
- Refer to the pinctrl documentation in the kernel for more info.
- Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
- Documentation/devicetree/bindings/pinctrl/renesas,pcf.yaml
In the Device Tree, the MDIO address is set by @x and the "reg =<x>;" For example, MDIO address of 0:

	phy0: ethernet-phy@0 {
		reg = <0>;

If using MII (not RGMII), do not include output-enable; in txc{ } in your Device Tree. For RGMII, TX_CLK is always an output. But for MII, TX_CLK pin needs to be an input, so output-enable should not be set.

Device Tree Examples

Expand

title	Example of enabling MII mode for RZ/G2L

Ethernet node for MII mode

&eth0 {
	pinctrl-0 = <&eth0_mii_pins>;
	pinctrl-names = "default";
	phy-handle = <&phy0>;
	phy-mode = "mii";
	status = "okay";

	phy0: ethernet-phy@7 {
		compatible = "ethernet-phy-id0022.1640",
			     "ethernet-phy-ieee802.3-c22";
		reg = <7>;
		rxc-skew-psec = <2400>;
		txc-skew-psec = <2400>;
		rxdv-skew-psec = <0>;
		txdv-skew-psec = <0>;
		rxd0-skew-psec = <0>;
		rxd1-skew-psec = <0>;
		rxd2-skew-psec = <0>;
		rxd3-skew-psec = <0>;
		txd0-skew-psec = <0>;
		txd1-skew-psec = <0>;
		txd2-skew-psec = <0>;
		txd3-skew-psec = <0>;

		interrupt-parent = <&pinctrl>;
		interrupts = <RZG2L_GPIO(1, 0) IRQ_TYPE_LEVEL_LOW>;
	};
};

&eth1 {
	pinctrl-0 = <&eth1_mii_pins>;
	pinctrl-names = "default";
	phy-handle = <&phy1>;
	phy-mode = "mii";
	status = "okay";

	phy1: ethernet-phy@7 {
		compatible = "ethernet-phy-id0022.1640",
			     "ethernet-phy-ieee802.3-c22";
		reg = <7>;
		rxc-skew-psec = <2400>;
		txc-skew-psec = <2400>;
		rxdv-skew-psec = <0>;
		txdv-skew-psec = <0>;
		rxd0-skew-psec = <0>;
		rxd1-skew-psec = <0>;
		rxd2-skew-psec = <0>;
		rxd3-skew-psec = <0>;
		txd0-skew-psec = <0>;
		txd1-skew-psec = <0>;
		txd2-skew-psec = <0>;
		txd3-skew-psec = <0>;

		interrupt-parent = <&pinctrl>;
		interrupts = <RZG2L_GPIO(1, 1) IRQ_TYPE_LEVEL_LOW>;
	};
};

Pin Setup

&pinctrl {

	eth0_mii_pins: eth0 {
		pinmux = <RZG2L_PORT_PINMUX(28, 1, 1)>, /* ET0_LINKSTA */
			 <RZG2L_PORT_PINMUX(27, 1, 1)>, /* ET0_MDC */
			 <RZG2L_PORT_PINMUX(28, 0, 1)>, /* ET0_MDIO */
			 <RZG2L_PORT_PINMUX(20, 0, 1)>, /* ET0_TXC */
			 <RZG2L_PORT_PINMUX(20, 1, 1)>, /* ET0_TX_CTL */
			 <RZG2L_PORT_PINMUX(20, 2, 1)>, /* ET0_TXD0 */
			 <RZG2L_PORT_PINMUX(21, 0, 1)>, /* ET0_TXD1 */
			 <RZG2L_PORT_PINMUX(21, 1, 1)>, /* ET0_TXD2 */
			 <RZG2L_PORT_PINMUX(22, 0, 1)>, /* ET0_TXD3 */
			 <RZG2L_PORT_PINMUX(22, 1, 1)>,	/* ETH0_TX_ERR */
			 <RZG2L_PORT_PINMUX(23, 0, 1)>,	/* ETH0_TX_COL */
			 <RZG2L_PORT_PINMUX(23, 1, 1)>, /* ETH0_TX_CRS */
			 <RZG2L_PORT_PINMUX(24, 0, 1)>, /* ET0_RXC */
			 <RZG2L_PORT_PINMUX(24, 1, 1)>, /* ET0_RX_CTL */
			 <RZG2L_PORT_PINMUX(25, 0, 1)>, /* ET0_RXD0 */
			 <RZG2L_PORT_PINMUX(25, 1, 1)>, /* ET0_RXD1 */
			 <RZG2L_PORT_PINMUX(26, 0, 1)>, /* ET0_RXD2 */
			 <RZG2L_PORT_PINMUX(26, 1, 1)>, /* ET0_RXD3 */
			 <RZG2L_PORT_PINMUX(27, 0, 1)>; /* ETH0_RX_ERR */
	};

	eth1_mii_pins: eth1 {
		pinmux = <RZG2L_PORT_PINMUX(37, 2, 1)>, /* ET1_LINKSTA */
			 <RZG2L_PORT_PINMUX(37, 0, 1)>, /* ET1_MDC */
			 <RZG2L_PORT_PINMUX(37, 1, 1)>, /* ET1_MDIO */
			 <RZG2L_PORT_PINMUX(29, 0, 1)>, /* ET1_TXC */
			 <RZG2L_PORT_PINMUX(29, 1, 1)>, /* ET1_TX_CTL */
			 <RZG2L_PORT_PINMUX(30, 0, 1)>, /* ET1_TXD0 */
			 <RZG2L_PORT_PINMUX(30, 1, 1)>, /* ET1_TXD1 */
			 <RZG2L_PORT_PINMUX(31, 0, 1)>, /* ET1_TXD2 */
			 <RZG2L_PORT_PINMUX(31, 1, 1)>, /* ET1_TXD3 */
			 <RZG2L_PORT_PINMUX(32, 0, 1)>, /* ETH1_TX_ERR */
			 <RZG2L_PORT_PINMUX(32, 1, 1)>, /* ETH1_TX_COL */
			 <RZG2L_PORT_PINMUX(33, 0, 1)>, /* ETH1_TX_CRS */
			 <RZG2L_PORT_PINMUX(33, 1, 1)>, /* ET1_RXC */
			 <RZG2L_PORT_PINMUX(34, 0, 1)>, /* ET1_RX_CTL */
			 <RZG2L_PORT_PINMUX(34, 1, 1)>, /* ET1_RXD0 */
			 <RZG2L_PORT_PINMUX(35, 0, 1)>, /* ET1_RXD1 */
			 <RZG2L_PORT_PINMUX(35, 1, 1)>, /* ET1_RXD2 */
			 <RZG2L_PORT_PINMUX(36, 0, 1)>, /* ET1_RXD3 */
			 <RZG2L_PORT_PINMUX(36, 1, 1)>; /* ETH1_RX_ERR */
	};
};

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RZ/G2H, G2M, G2N, G2E:
- CONFIG_xxxPWM_RZ_MTU3=y
- drivers/pwm/pwm-rz-mtu3.c
RZ/G2L, G2LC, G2UL, V2L:
- CONFIG_xxxGPT_RZG2L=y
- drivers/pwm/gpt-rzg2l.c

Notes

Device Tree Examples

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RZ/G2H, G2M, G2N, G2E:
- drivers/thermal/rcar_gen3__thermal.c
- CONFIG_RCAR_GEN3_THERMAL=y
RZ/G2L, G2LC, G2UL, V2L:
- drivers/thermal/rzg2l_thermal.c
- CONFIG_RZG2L_THERMAL=y
RZ/V2H
- Supported on AI_SDK 5.0 and later
- Enabled by default
- CONFIG_RZG2L_THERMAL=y

Notes

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