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Prerequisites
A compatible JTAG hardware debugger device is required. Different JTAG devices can have slightly different procedure.
As an example, following guidance is for:

• Segger J-Link debug probesDebug Probe
  • J-Link Website
  • J-Link BASE, J-Link PLUS, J-Link PRO
  • Requires 20-to-10 pin adapter
• ARM-JTAG-20-10 Adapter (Mouser) (
  • 🛒 Olimex
  • 🛒 Mouser
  • 🛒 Digi-Key
  )

Hardware setup

Most RZ development boards has 10 pin JTAG header, so a JTAG converter (20pin-10pin) might be required depending on what JTAG adapter you are using. For example the Olimex ARM-JTAG-20-10. can be used to convert from 20-pin to 10-pin.

After connecting the devices as per guide in the previous section, follow below instructions to use OpenOCD and JTAG debugger. You must change the switches setting on development board to enable the JTAG debugging feature. The switches setting may be different for each development board. Please refer to the relevant board manual or user guide for detailed information.

SMARC RZ/G2L-LC-UL, RZ/Five board

Change switches as per below.

Image Removed

• SW1: OFF - OFF

EK874 RZ/G2E board

Change switches as per below. Note that board version 3 (Rev C) or later must be used.

Image Removed

• SW12: change bit 4 and 5 to OFF to enable JTAG
• SW50: change to (2-3) side
• SW51: change to (1-2) side

HiHope RZ/G2M-N-H board

Change switches as per below. Note that board rev. 3 or later must be used.

Image Removed Image Removed Image Removed

• SW1003: change bit 4 to OFF to enable JTAG
• SW305: change to (2-3) side
• SW2405: change to (1-2) side

Download and Build OpenOCD

To build OpenOCD you can use this script found in the https://github.com/renesas-rz/rzg_openocd repository.

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• Tigard Open Source Tool
  • https://github.com/tigard-tools/tigard
  • https://www.crowdsupply.com/securinghw/tigard
  • Includes correct 10-pin JTAG cable (no adapter is needed)
  • Requires USB-C cable for power and data (not included)
  • 🛒 ($49) https://www.mouser.com/ProductDetail/Securing-Hardware/TIGARD-V1?qs=aP1CjGhiNiFnjSEE%2FnXyEw%3D%3D
  • 🛒 ($49) https://1bitsquared.com/products/tigard

Hardware setup

Most RZ development boards has 10 pin JTAG header, so a JTAG converter (20pin-10pin) might be required depending on what JTAG adapter you are using. For example the Olimex ARM-JTAG-20-10. can be used to convert from 20-pin to 10-pin.

After connecting the devices as per guide in the previous section, follow below instructions to use OpenOCD and JTAG debugger. You must change the switches setting on development board to enable the JTAG debugging feature. The switches setting may be different for each development board. Please refer to the relevant board manual or user guide for detailed information.

SMARC RZ/G2L-LC-UL, RZ/Five board

Change switches as per below.

Image Added

• SW1: OFF - OFF

EK874 RZ/G2E board

Change switches as per below. Note that board version 3 (Rev C) or later must be used.

Image Added

• SW12: change bit 4 and 5 to OFF to enable JTAG
• SW50: change to (2-3) side
• SW51: change to (1-2) side

HiHope RZ/G2M-N-H board

Change switches as per below. Note that board rev. 3 or later must be used.

Image Added    Image Added    Image Added

• SW1003: change bit 4 to OFF to enable JTAG
• SW305: change to (2-3) side
• SW2405: change to (1-2) side

Tigard Switch Setting

If you are using a Tigard, set the TARGET switch to 1v8

Image Added

and the MODE switch to JTAG

Image Added

Download and Build OpenOCD

To build OpenOCD you can use this script found in the https://github

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.com/renesas-rz/rzg_openocd

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 repository.

$ wget https://raw.githubusercontent.com/renesas-rz/rzg_openocd/master/0003-target-aarch64-enable-disable-mmu-new-commands.patchbuild_openocd.sh
$ wget https://raw.githubusercontent.com/renesas-rz/rzg_openocd/master/00040001-tcl-target-aarch64-Add-coderenesas_rz_g2-Rename-to-invaldaterenesas_rz-theand-instructionad.patch
$ wget https://raw.githubusercontent.com/renesas-rz/rzg_openocd/master/0005-tcl-target-renesas_rz-add-hwthread-and-coreid0002-target-aarch64-MRS-MSR-support-for-system-register-a.patch
$ chmod +x ./build_openocd
$ export GIT_SSL_NO_VERIFY=1    # Avoid GIT error: server certificate verification failed
$ ./build_openocd

Or manually follow the steps in that script:

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wget https://raw.githubusercontent.com/renesas-rz/rzg_openocd/master/0003-target-aarch64-enable-disable-mmu-new-commands.patch
$ wget https://raw.githubusercontent.com/renesas-rz/rzg_openocd

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/master/

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0004-target-aarch64-Add-code-to-invaldate-the-instruction.patch
$ wget https://raw.githubusercontent.com/renesas-rz/rzg_openocd/master/0005-tcl-target-renesas_rz-add-hwthread-and-coreid.patch
$ chmod +x ./build_openocd.sh
$ export GIT_SSL_NO_VERIFY=1    # Avoid GIT error: server certificate verification failed
$ ./build_openocd.sh

Or manually follow the steps in that script:

• https://github.com/renesas-rz/rzg_openocd/blob/master/build_openocd

The OpenOCD binaries can be found in the openocd/installdir/bin directory.

In the configuration, options that are commonly needed are --enable-ftdi to ensure ftdi related function will be built. Same for J-Link, with --enable-jlink, however both should be recognized and added automatically during the configuration phase.

Note - The patch is not strictly needed. It slows down the download operations

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The OpenOCD binaries can be found in the openocd/installdir/bin directory.

In the configuration, options that are commonly needed are --enable-ftdi to ensure ftdi related function will be built. Same for J-Link, with --enable-jlink, however both should be recognized and added automatically during the configuration phase.

Note - The patch is not strictly needed. It slows down the download operations but it is required if an existing code in memory has to be replaced by using the JTAG.

Run OpenOCD

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has to be replaced by using the JTAG.

Run OpenOCD

OpenOCD provides many setting scripts for many JTAG debugger and development boards under directory share/openocd/scripts/.

Normally two suitable scripts has to be chosen, one for Debugger Configuration and one for the Development Board or SoC Configuration.

Debugger Configuration File

• To debug with J-Link, the following script is available: share/openocd/scripts/interface/jlink.cfg
• To debug with Tigard, the following script is available: share/openocd/scripts/

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• interface/ftdi/tigard.cfg

Development Board or SoC Configuration File

• The Device configuration file for the RZ family is share/openocd/scripts/target/renesas_rz.cfg
• Note: In the Official OpenOCD repository, the file name is renesas_rz_g2.cfg. However, in the patches you downloaded and ran, we renamed it to renesas_rz.cfg. We plan to mainline this change back into the official openocd repository eventually 

Development Board or SoC Configuration (SoC selection)

Different

To debug with Flyswatter2 the following scripts is available:

interface/ftdi/flyswatter2.cfg

To debug with J-Link, instead:

interface/jlink.cfg

Then for the RZ/G2 family:

target/renesas_rz.cfg

Finally different commands have to be used to select different devices belonging to the RZ /G2 family:

• SMARC RZ/G2L board: "set SOC G2L"            (default), i.e. -c can be omitted
• SMARC RZ/G2LC board: "set SOC G2LC"
• SMARC RZ/G2UL board: "set SOC G2UL"
• SMARC RZ/V2L board: "set SOC V2L"
• SMARC II RZ/G3S board: "set SOC G3S"
• EK874 RZ/G2E board: "set SOC G2EG2E"
• HiHope RZ/G2M board: "set SOC G2M"
• HiHope RZ/G2N board: "set SOC G2N"
• HiHope RZ/G2M G2H board: "set SOC G2M
• HiHope RZ/G2N board: set SOC G2N
• HiHope RZ/G2H board: set SOC G2H
• G2H"

Example Command Lines:

Example to run OpenOCD and attach to a RZ/G2L device using a Segger J-Link JTAG adapter:

$ cd installdir
$ sudo bin/openocd -f share/openocd/scripts/interface/jlink.cfg -c "set SOC G2L" -f share/openocd/scripts/target/renesas_rz.cfg

Example So, for example to run OpenOCD and attach to a RZ/G2L device using a Segger J-Link Tigard JTAG adapter:

$ cd installdir
$ sudo bin/openocd -f share/openocd/scripts/interface/ftdi/jlinktigard.cfg -c "set SOC G2L" -f share/openocd/scripts/target/target/renesas_rz.cfg

RZ/Five uses a different configuration file (renesas_rz_five.cfg

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)

Example to run OpenOCD and attach to a In case of RZ/Five device using a Segger J-LinkJTAG adapter:

$ cd installdir
$ sudo bin/openocd -f share/openocd/scripts/interface/jlink.cfg -f share/openocd/scripts/target/renesas_rz_five.cfg

Please note that there's a way to avoid the usage of sudo by making sure that both the user and the debugger devices used belong to the dialout/plugdev groups.

JTAG Adapter Clock Speed

You can modify the renesas_rz_*.cfg configure file to tweak the clock speed (default 4MHz), for example to increase it to 15MHz:

adapter speed 15000

Verify Connection

If openocd command succeeds, a message like these below appears:

Open On-Chip Debugger 0.12.0+dev-01565-g5622ada82 (2024-04-10-13:59)
Licensed under GNU GPL v2
For bug reports, read
	http://openocd.org/doc/doxygen/bugs.html
G2L
	G2L - 0 CA57(s), 2 CA55(s), 0 CA53(s), 0 CR7(s),  1 CM33(s)
	Boot Core - CA55

r9a07g044l.cpu
SMP targets: r9a07g044l.a55.0 r9a07g044l.a55.1
init_reset
Info : Listening on port 6666 for tcl connections
Info : Listening on port 4444 for telnet connections
Info : J-Link Lite V10 compiled Jan 30 2023 11:28:07
Info : Hardware version: 10.10
Info : VTarget = 1.761 V
Info : clock speed 4000 kHz
Info : JTAG tap: r9a07g044l.cpu tap/device found: 0x6ba00477 (mfg: 0x23b (ARM Ltd), part: 0xba00, ver: 0x6)
Info : r9a07g044l.a55.0: hardware has 6 breakpoints, 4 watchpoints
Info : r9a07g044l.a55.0 cluster 0 core 0 multi core
Info : [r9a07g044l.a55.0] Examination succeed
Info : [r9a07g044l.axi_ap] Examination succeed
Info : starting gdb server for r9a07g044l.a55.0 on 3333
Info : Listening on port 3333 for gdb connections
Info : starting gdb server for r9a07g044l.m33 on 3334
Info : Listening on port 3334 for gdb connections
Info : gdb port disabled

Open On-Chip Debugger 0.11.0+dev-00663-gd1e14abdb-dirty (2022-05-10-07:54) 
Licensed under GNU GPL v2 
For bug reports, read 
        http://openocd.org/doc/doxygen/bugs.html 
r9A07g043u.

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cpu Info : 
Listening on port 6666 for tcl connections 
Info : Listening on port 4444 for telnet connections 
Info : J-Link Lite V9 compiled Feb 2 2021 16:32:48

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Info : Hardware version: 9.00

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Info : VTarget = 1.819 V

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Info : clock speed 4000 kHz

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Info : JTAG tap: r9A07g043u.cpu tap/device found: 0x1000563d (mfg: 0x31e (Andes Technology Corporation), part: 0x0005, ver: 0x1)

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Info : datacount=4 progbufsize=8

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 Info : Examined RISC-V core; found 1 harts

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Info : hart 0: XLEN=64, misa=0x800000000094312d

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Info : starting gdb server for r9A07g043u.cpu on 3333

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Info : Listening on port 3333 for gdb connections

Note that the "DAP transaction stalled" messages are normal and do not affect the functionality.

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