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This page contains helpful notes about Device Tree configurations and Device Driver details

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title	Example of RGB Panel on RZ/G2L

Configure pins

&pinctrl {
	du_pins: du {
		data {
			pinmux = <RZG2L_PORT_PINMUX(7,  2, 1)>,
				 <RZG2L_PORT_PINMUX(8,  0, 1)>,
				 <RZG2L_PORT_PINMUX(8,  1, 1)>,
				 <RZG2L_PORT_PINMUX(8,  2, 1)>,
				 <RZG2L_PORT_PINMUX(9,  0, 1)>,
				 <RZG2L_PORT_PINMUX(9,  1, 1)>,
				 <RZG2L_PORT_PINMUX(10, 0, 1)>,
				 <RZG2L_PORT_PINMUX(10, 1, 1)>,
				 <RZG2L_PORT_PINMUX(11, 0, 1)>,
				 <RZG2L_PORT_PINMUX(11, 1, 1)>,
				 <RZG2L_PORT_PINMUX(12, 0, 1)>,
				 <RZG2L_PORT_PINMUX(12, 1, 1)>,
				 <RZG2L_PORT_PINMUX(13, 0, 1)>,
				 <RZG2L_PORT_PINMUX(13, 1, 1)>,
				 <RZG2L_PORT_PINMUX(13, 2, 1)>,
				 <RZG2L_PORT_PINMUX(14, 0, 1)>,
				 <RZG2L_PORT_PINMUX(14, 1, 1)>,
				 <RZG2L_PORT_PINMUX(15, 0, 1)>,
				 <RZG2L_PORT_PINMUX(15, 1, 1)>,
				 <RZG2L_PORT_PINMUX(16, 0, 1)>,
				 <RZG2L_PORT_PINMUX(16, 1, 1)>,
				 <RZG2L_PORT_PINMUX(17, 0, 1)>,
				 <RZG2L_PORT_PINMUX(17, 1, 1)>,
				 <RZG2L_PORT_PINMUX(17, 2, 1)>;
		};

		sync {
			pinmux = <RZG2L_PORT_PINMUX(6, 1, 1)>, /* HSYNC */
				 <RZG2L_PORT_PINMUX(7, 0, 1)>; /* VSYNC */
		};

		de {
			pinmux = <RZG2L_PORT_PINMUX(7, 1, 1)>; /* DE */
		};
		
		clk {
			pinmux = <RZG2L_PORT_PINMUX(6, 0, 1)>; /* CLK */
		};
	};
};

Add a rgb-dummy device

	rgb-dummy {
		compatible = "renesas,rgb-dummy";
		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;
				rgb_in: endpoint {
					remote-endpoint = <&du_out_rgb>;
					};
				};
				port@1 {
					reg = <1>;
						rgb_out: endpoint {
							remote-endpoint = <&panel_in>;
						};
				};
			};
		};

Add panel device node:

panel {
	/* 
	* Define code for panel here such as compatible, backlight, power,...
	* Can refer drivers/gpu/drm/panel/panel-simple.c
	*/
	port {
		panel_in: endpoint {
			remote-endpoint = <&rgb_out>;
		};
	};
};

We want the MIPI DSI driver disabled

&dsi0 {
	status = "disabled";
};

Add endpoint for DU RGB out:

&du {
	pinctrl-0 = <&du_pins>;
	pinctrl-names = "default";

	ports {
		port@0 {
			du_out_rgb: endpoint {
				remote-endpoint = <&rgb_in>;
			};
		};
	};
 };

Audio

Linux Drivers

RZ/G2H, G2M, G2N, G2E: rz_linux-cip/sound/soc/sh/rcar/*.c
RZ/G2L, G2LC, G2UL, V2L: rz_linux-cip/sound/soc/sh/rz-ssi.c

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Expand

title	Example of MAX9867 codec with MAX98390 Amplifier for RZ/G2L

Here is an example of a MAX9867 on SSI channel 3, using I2C-3. MAX98390 Amplifier on I2C-2.

This is for the Linux-5.10 kernel. For the older Linux-4.19 kernel, there are some differences.

Pin Setup

&pinctrl {

	/* MAX98390 Amplifier */
	i2c2_pins: i2c2 {
		pinmux = <RZG2L_PORT_PINMUX(42, 3, 1)>, /* SDA */
			 <RZG2L_PORT_PINMUX(42, 4, 1)>; /* SCL */
	};

	/* MAX9867 Codec */
	i2c3_pins: i2c3 {
		pinmux = <RZG2L_PORT_PINMUX(18, 0, 3)>, /* SDA */
			 <RZG2L_PORT_PINMUX(18, 1, 3)>; /* SCL */
	};

	ssi3_pins: ssi3 {
	pinmux = <RZG2L_PORT_PINMUX(31, 0, 5)>, /* BCK */
		<RZG2L_PORT_PINMUX(31, 1, 5)>, /* RCK */
		<RZG2L_PORT_PINMUX(32, 0, 5)>, /* TXD */
		<RZG2L_PORT_PINMUX(32, 1, 5)>; /* RXD */
	};
};

Enable SSI channel

&ssi3 {
	pinctrl-0 = <&ssi3_pins>;
	pinctrl-names = "default";

	#sound-dai-cells = <1>;
	status = "okay";
};

Create a node for the MAX9867

	my_snd: sound {
		compatible = "simple-audio-card";
		simple-audio-card,widgets = "Speaker", "Ext Spk";

		simple-audio-card,routing =
		"Ext Spk", "BE_OUT";
		"Ext Spk", "LOUT",
		"Ext Spk", "ROUT";

		/* MAX98390 Amplifier */
		simple-audio-card,dai-link@0{
			format = "i2s";
			bitclock-master = <&cpu_dai3>;
			frame-master = <&cpu_dai3>;
			mclk-fs = <256>;
			cpu_dai3: cpu {
				sound-dai = <&ssi3>;
			};

			codec_dai3: codec {
				sound-dai = <&max98390>;
				clocks = <&mclk>;
			};
		};

		/* MAX9867 Codec */
		simple-audio-card,dai-link@1{
			format = "i2s";
			bitclock-master = <&cpu_dai0>;
			frame-master = <&cpu_dai0>;
			mclk-fs = <256>;
			cpu_dai0: cpu {
				sound-dai = <&ssi0>;
			};

			codec_dai0: codec {
				sound-dai = <&max9867>;
				clocks = <&mclk>;
			};
		};
	};

I2C node for the Codec and Amp

&i2c2 {
	pinctrl-0 = <&i2c2_pins>;
	pinctrl-names = "default";

	status = "okay";
	clock-frequency = <400000>;

	/* MAX98390 Amplifier */
	max98390: codec@3d {
		status = "okay";
		compatible = "maxim,max98390";
		#sound-dai-cells = <0>;
		reg = <0x3d>;
	};
};

&i2c3 {
	pinctrl-0 = <&i2c3_pins>;
	pinctrl-names = "default";

	status = "okay";
	clock-frequency = <400000>;

	/* MAX9867 Codec */
	max9867: codec@18 {
		status = "okay";
		compatible = "maxim,max9867";
		#sound-dai-cells = <0>;
		reg = <0x18>;
	};
};

Camera

Linux Drivers

RZ/G2H, G2M, G2N, G2E:
- CONFIG_xxx=y
RZ/G2L, G2LC, G2UL, V2L:
- CONFIG_xxx=y

...

(see device tree for evaluation board)

Ethernet

Linux Drivers

RZ/G2H, G2M, G2N, G2E, G2L, G2LC, G2UL, V2L:
- rz_linux-cip/drivers/net/ethernet/renesas/ (ravb_main.c, ravb_ptp.c)
- Documentation/devicetree/bindings/net/renesas,etheravb.yaml
- CONFIG_NET_VENDOR_RENESAS=y
- # CONFIG_SH_ETH is not set
- CONFIG_RAVB=y

...

Expand

title	Example of enabling MII mode for RZ/G2L

Ethernet node for MII mode

&eth0 {
	pinctrl-0 = <&eth0_mii_pins>;
	pinctrl-names = "default";
	phy-handle = <&phy0>;
	phy-mode = "mii";
	status = "okay";

	phy0: ethernet-phy@7 {
		compatible = "ethernet-phy-id0022.1640",
			     "ethernet-phy-ieee802.3-c22";
		reg = <7>;
		rxc-skew-psec = <2400>;
		txc-skew-psec = <2400>;
		rxdv-skew-psec = <0>;
		txdv-skew-psec = <0>;
		rxd0-skew-psec = <0>;
		rxd1-skew-psec = <0>;
		rxd2-skew-psec = <0>;
		rxd3-skew-psec = <0>;
		txd0-skew-psec = <0>;
		txd1-skew-psec = <0>;
		txd2-skew-psec = <0>;
		txd3-skew-psec = <0>;

		interrupt-parent = <&pinctrl>;
		interrupts = <RZG2L_GPIO(1, 0) IRQ_TYPE_LEVEL_LOW>;
	};
};

&eth1 {
	pinctrl-0 = <&eth1_mii_pins>;
	pinctrl-names = "default";
	phy-handle = <&phy1>;
	phy-mode = "mii";
	status = "okay";

	phy1: ethernet-phy@7 {
		compatible = "ethernet-phy-id0022.1640",
			     "ethernet-phy-ieee802.3-c22";
		reg = <7>;
		rxc-skew-psec = <2400>;
		txc-skew-psec = <2400>;
		rxdv-skew-psec = <0>;
		txdv-skew-psec = <0>;
		rxd0-skew-psec = <0>;
		rxd1-skew-psec = <0>;
		rxd2-skew-psec = <0>;
		rxd3-skew-psec = <0>;
		txd0-skew-psec = <0>;
		txd1-skew-psec = <0>;
		txd2-skew-psec = <0>;
		txd3-skew-psec = <0>;

		interrupt-parent = <&pinctrl>;
		interrupts = <RZG2L_GPIO(1, 1) IRQ_TYPE_LEVEL_LOW>;
	};
};

Pin Setup

&pinctrl {

	eth0_mii_pins: eth0 {
		pinmux = <RZG2L_PORT_PINMUX(28, 1, 1)>, /* ET0_LINKSTA */
			 <RZG2L_PORT_PINMUX(27, 1, 1)>, /* ET0_MDC */
			 <RZG2L_PORT_PINMUX(28, 0, 1)>, /* ET0_MDIO */
			 <RZG2L_PORT_PINMUX(20, 0, 1)>, /* ET0_TXC */
			 <RZG2L_PORT_PINMUX(20, 1, 1)>, /* ET0_TX_CTL */
			 <RZG2L_PORT_PINMUX(20, 2, 1)>, /* ET0_TXD0 */
			 <RZG2L_PORT_PINMUX(21, 0, 1)>, /* ET0_TXD1 */
			 <RZG2L_PORT_PINMUX(21, 1, 1)>, /* ET0_TXD2 */
			 <RZG2L_PORT_PINMUX(22, 0, 1)>, /* ET0_TXD3 */
			 <RZG2L_PORT_PINMUX(22, 1, 1)>,	/* ETH0_TX_ERR */
			 <RZG2L_PORT_PINMUX(23, 0, 1)>,	/* ETH0_TX_COL */
			 <RZG2L_PORT_PINMUX(23, 1, 1)>, /* ETH0_TX_CRS */
			 <RZG2L_PORT_PINMUX(24, 0, 1)>, /* ET0_RXC */
			 <RZG2L_PORT_PINMUX(24, 1, 1)>, /* ET0_RX_CTL */
			 <RZG2L_PORT_PINMUX(25, 0, 1)>, /* ET0_RXD0 */
			 <RZG2L_PORT_PINMUX(25, 1, 1)>, /* ET0_RXD1 */
			 <RZG2L_PORT_PINMUX(26, 0, 1)>, /* ET0_RXD2 */
			 <RZG2L_PORT_PINMUX(26, 1, 1)>, /* ET0_RXD3 */
			 <RZG2L_PORT_PINMUX(27, 0, 1)>; /* ETH0_RX_ERR */
	};

	eth1_mii_pins: eth1 {
		pinmux = <RZG2L_PORT_PINMUX(37, 2, 1)>, /* ET1_LINKSTA */
			 <RZG2L_PORT_PINMUX(37, 0, 1)>, /* ET1_MDC */
			 <RZG2L_PORT_PINMUX(37, 1, 1)>, /* ET1_MDIO */
			 <RZG2L_PORT_PINMUX(29, 0, 1)>, /* ET1_TXC */
			 <RZG2L_PORT_PINMUX(29, 1, 1)>, /* ET1_TX_CTL */
			 <RZG2L_PORT_PINMUX(30, 0, 1)>, /* ET1_TXD0 */
			 <RZG2L_PORT_PINMUX(30, 1, 1)>, /* ET1_TXD1 */
			 <RZG2L_PORT_PINMUX(31, 0, 1)>, /* ET1_TXD2 */
			 <RZG2L_PORT_PINMUX(31, 1, 1)>, /* ET1_TXD3 */
			 <RZG2L_PORT_PINMUX(32, 0, 1)>, /* ETH1_TX_ERR */
			 <RZG2L_PORT_PINMUX(32, 1, 1)>, /* ETH1_TX_COL */
			 <RZG2L_PORT_PINMUX(33, 0, 1)>, /* ETH1_TX_CRS */
			 <RZG2L_PORT_PINMUX(33, 1, 1)>, /* ET1_RXC */
			 <RZG2L_PORT_PINMUX(34, 0, 1)>, /* ET1_RX_CTL */
			 <RZG2L_PORT_PINMUX(34, 1, 1)>, /* ET1_RXD0 */
			 <RZG2L_PORT_PINMUX(35, 0, 1)>, /* ET1_RXD1 */
			 <RZG2L_PORT_PINMUX(35, 1, 1)>, /* ET1_RXD2 */
			 <RZG2L_PORT_PINMUX(36, 0, 1)>, /* ET1_RXD3 */
			 <RZG2L_PORT_PINMUX(36, 1, 1)>; /* ETH1_RX_ERR */
	};
};

USB

Linux Drivers

RZ/G2H, G2M, G2N, G2E:
RZ/G2L, G2LC, G2UL, V2L:

...

Expand

title	RZ/G2L SMARC Device Tree Example

/ {
	reg_3p3v: regulator1 {
		compatible = "regulator-fixed";

		regulator-name = "fixed-3.3V";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-boot-on;
		regulator-always-on;
	};

	vccq_sdhi1: regulator-vccq-sdhi1 {
		compatible = "regulator-gpio";
		regulator-name = "SDHI1 VccQ";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <3300000>;
		gpios-states = <1>;
		states = <3300000 1>, <1800000 0>;
	};
};

&sdhi1 {
	pinctrl-0 = <&sdhi1_pins>;
	pinctrl-1 = <&sdhi1_pins_uhs>;
	pinctrl-names = "default", "state_uhs";

	vmmc-supply = <&reg_3p3v>;
	vqmmc-supply = <&vccq_sdhi1>;
	bus-width = <4>;
	sd-uhs-sdr50;
	sd-uhs-sdr104;
	status = "okay";
};

eMMC

Linux Drivers

RZ/G2H, G2M, G2N, G2E:
RZ/G2L, G2LC, G2UL, V2L:
- driver/mmc/host/renesas_sdhi.h
- driver/mmc/host/renesas_sdhi_core.c
- driver/mmc/host/renesas_sdhi_internal_dmac.c
- driver/mmc/host/tmio_mmc.h
- driver/mmc/host/tmio_mmc_core.c
- CONFIG_MMC_SDHI=y
- CONFIG_MMC_SDHI_INTERNAL_DMAC=y (selected automatically by MMC_SDHI)
- CONFIG_MMC_TMIO_CORE=y (selected automatically by MMC_SDHI)

...

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