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PTX130W host interface communication (e.g. SPI access) to access test register:
0xA6 | SYS_TEST_CONTROL0_REG | STD | 0x00 | ||||||||
7 | 7 | RFU | 0 | RO | Reserved | ||||||
6 | 6 | DMEM_BIST_ERR | 0 | RO | Active high indication that an error was detected during DMEM BIST mode, only valid when bist_en and bist_end are both high | ||||||
5 | 5 | DMEM_BIST_END | 0 | RO | Active high indication that DMEM BIST has finished, cleared when bist_en is reset | ||||||
4 | 4 | DMEM_BIST_EN | 0 | RW | Active high enable of DMEM BIST mode | ||||||
3 | 3 | RFU | 0 | RO | Reserved | ||||||
2 | 2 | CMEM_BIST_ERR | 0 | RO | Active high indication that an error was detected during CMEM BIST mode, only valid when bist_en and bist_end are both high | ||||||
1 | 1 | CMEM_BIST_END | 0 | RO | Active high indication that CMEM BIST has finished, cleared when bist_en is reset | ||||||
0 | 0 | CMEM_BIST_EN | 0 | RW | Active high enable of CMEM BIST mode |
Test execution and resultvalidation
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struct ptxPlat *plat;
struct ptxPlat_ConfigPars ip = {.baudRate = 1000000, .flowControl = 1};
st = ptxPLAT_AllocAndInit(&plat, &ip);
uint8_t tx0[] = {0xB0, 0xa6, 0x11};
uint8_t *tx[] = {tx0};
uint8_t rx0[48];
uint8_t *rx[] = {rx0};
size_t txL[] = {3};
st = ptxPLAT_TRx(plat, tx, txL, 1, NULL, NULL, 0);
ptxCommon_PrintF("Start test: %04X\n", st);
ptxPLAT_Sleep(plat, 101);
uint8_t tx1[] = {0x30, 0xA6, 0};
*txL = sizeof(tx1);
*tx = tx1;
size_t rxL0 = 1;
size_t *rxL[] = {&rxL0};
*rx0 = 0;
st = ptxPLAT_TRx(plat, tx, txL, 1, rx, rxL, 1);
uint8_t result = **rx;
bool error = ((result & 7) != 3) || ((result & 0x70) != 0x30);
ptxCommon_PrintF(Result: %04X %04X %s\n", st, result, (error ? "ERROR":"PASS"));
ptxPLAT_Deinit(plat);
while (1);
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